The present invention relates to a clock recovering circuit, and more particularly, to a clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof.
A clock recovering circuit is commonly applied to a Partial-Response Maximum-Likelihood (PRML) read channel. Please refer to FIG. 1. FIG. 1 shows a first related art clock recovering circuit 100. The clock recovering circuit 100 includes an analog-to-digital converter (ADC) 110, a phase detector 120, a loop filter 130, a digital-to-analog converter (DAC) 140, and a voltage controlled oscillator (VCO) 150. The clock recovering circuit 100 utilizes the ADC 110 to sample an analog input signal SA, an Eight-to-Fourteen Modulation (EFM) signal for example, according to a recovering clock CLKout generated from the VCO 150, and then converts the analog input signal SA into a digital output signal SD having a plurality of digital values. The above-mentioned recovering clock CLKout is generated under the operation of the phase detector 120, the loop filter 130, the DAC 140, and the VCO 150. The action of the above four elements is like a well-known phase locked loop (PLL), which is used to lock a correct recovering clock CLKout that is capable of driving the ADC 110 to sample the input analog SA at desired timing. In other words, the output digital data SD can be correctly generated by converting the analog data SA, which is sampled by the correctly-locked recovering clock CLKout, to digital sample values.
FIG. 2 shows a second related art clock recovering circuit 200. The clock recovering circuit 200 includes an ADC 210, a phase detector 220, a loop filter 230, a numerically controlled oscillator (NCO) 240, and a data interpolator 250. The ADC 210 utilizes a reference clock CLKref to sample an analog input signal SA, and then converts the analog signal SA to a digital signal SD having a plurality of digital values. Commonly, the reference clock CLKref is provided by a clock source such as a related art PLL. As one can see, the data interpolator 250 performs interpolation according to the digital signal SD and an index signal IΘ, which is utilized to provide information related to an amount of phase error due to the reference clock CLKref sampling the analog signal SA at erroneous timing. Since the phase error is notified by the index signal I⊖, the data interpolator 250, therefore, is capable of compensating the phase error through interpolating a plurality of digital values of the digital signal SD according to the index signal I⊖. That is, another digital signal SD′, which is ideally free of the phase error caused by the erroneous sampling timing, is outputted from the data interpolator 250.
The above-mentioned index signal I⊖ is generated under the operation of the phase detector 220, the loop filter 230 and the NCO 240, and the action of the above three elements is like a well-known digital phase locked loop (DPLL). Because the functionality and operation of the phase detector 220, loop filter 230, and NCO 240 are known to those skilled in the art, further discussion of their operation is omitted for the sake of brevity.
As one can see, the first related art clock recovering circuit 100 and the second related art clock recovering circuit 200 are both capable of generating the desired data, i.e., the output digital data SD and the digital signal SD′. The key difference is that the first related art clock recovering circuit 100 gets the desired data through tuning the recovering clock CLKout, and the second related art clock recovering circuit 200 acquires the desired data through tuning the incoming digital values.
However, as shown in FIG. 1, the first related art clock recovering circuit 100 utilizes the ADC 110, which is easily affected by noise and results in poor performance. In addition, in order to achieve better performance, a DAC having high resolution and a VCO having wide operation range are needed, which makes the first related art clock recovering circuit 100 not easy to implement. Concerning the second related art clock recovering circuit 200, it makes use of the data interpolator 250 to interpolate the desired digital data according to the non-linear input, that is, the digital signal SD. The data interpolator 250, generally speaking, is sure to occupy a large chip area, which makes it difficult to have a compact chip size. Furthermore, the interpolation result may include wrong values due to the non-linear input.